The present invention is generally directed to a method and apparatus for increasing the density of electronic components on integrated circuit chips. More particularly, the present invention relates to a method of improving the contact resistance between a metallization layer and the semiconductor material so as to eliminate the necessity of using excessively wide metallization patterns in the vicinity of contact holes or vias.
In the manufacture of integrated circuit chips, it is typically necessary to connect semiconductor material, such as silicon, to a metallization pattern which defines interconnections among various electronic devices on the circuit chip. This interconnection is made through contact holes or vias in a dielectric layer. To ensure that the interconnecting metal contacts as much of the semiconductor material at the bottom of the via as possible, the interconnecting metal pattern is provided with frames or buffer areas which totally surround the contact opening. By providing as large a contact area as possible, contact resistance is kept low. Furthermore, since the metal frame edges are over SiO.sub.2, etching of the metal pattern eliminates any possibility of etching the silicon at the bottom of the via. If such etching should occur, the shallow diode could be affected, since plasma etching of aluminum will also etch silicon. Alternatively, rather than providing metallization frames around each contact opening it is also possible to achieve the same effect simply by providing sufficiently wide metallization patterns. In either case, the object is to have the metallization pattern completely cover the contact opening. However, both of these methods of solving a contact resistance problem result in metallization patterns which are wider than necessary. More particularly, such wide metallization patterning places unnecessary limits on the circuit packing density. Moreover, even if interconnect metallizations were simply made narrower, it is noted that alignment problems for narrow interconnection metallization patterns are much more severe. For example, the use of narrow interconnect metal patterns generally requires precise alignment of the metallization over the contact opening. With narrow patterning, partial rather than complete contact with the underlying semiconductor material results in a significant increase in contact resistance.
Accordingly, it is seen that it is desirable for high packing density to not require that interconnection metal cover or frame the contact openings. This objective can be met by improved contact conductivity between the metallization and the semiconductor material. This also relaxes the alignment requirements considerably since the interlevel metallization mask need not be aligned perfectly with the contact window pattern.
When the interconnection metal does not cover the contact holes, there is a danger that etching of this metal will also remove a portion of the material at the bottom of the hole. Most etchant gasses that are used for delineating metal patterns will etch silicon which is typically at the base of such contact holes. It is, therefore, also desirable to have a metal which can serve as an etch stop to prevent this damage.